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Conference Highlights

In-Stat forums are a rare combination of breaking news, insightful analysis, and non-stop networking. FPF draws the audience you want to reach most—the industry’s best.

  • Hear the first public disclosures of new microprocessors, DSPs, and related embedded technologies, presented by their chief architects.
  • Includes two full-day seminars on todays hottest topics led by Microprocessor Report’s award-winning analysts.
  • Leading organizations to present on PC processors, server processors, low-power embedded processors, consumer embedded, imaging DSPs, and on the challenges of advanced semiconductor design.


Fall Processor Forum 2005: The Road to Multicore

Seminar Agenda

Monday, October 24
Implementing Low Power SoC Configurations—presented by Max Baron

Thursday, October 27
A Briefing on DSP Technology—presented by the market leaders and moderated by Max Baron

Seminar Schedule
7:30 Registration & continental breakfast
8:30 Seminar begins
10:00 Morning break (20 minutes)
12:00 Lunch (60 minutes)
2:40 Afternoon break (20 minutes)
4:30 Seminar ends Q & A follows

Conference Agenda
Tue, Oct. 25, 2005
9:00 Welcome and Intro
9:05 Keynote: Mike Fister, President & CEO, Cadence
9:50 Session 1: Multicore Processors
10:45 Break (25 minutes)
Session 1 continues
12:25 Lunch (80 minutes)
1:45 Special Presentation
2:15 Session Two: Innovative IP
3:10 Break (25 minutes)
3:35 Session Three: Processor IP for Multicore
5:30 Adjourn to Expo
Wed, Oct. 26, 2005
9:00 Welcome
9:05 Keynote—Herb Sutter, Software Architect,
Microsoft Developer Division
9:50 Session Four: Building Systems with Multicore Processors
10:35 Break (25 minutes)
Session Four continues
12:15 Lunch (75 minutes)
1:30 Session Four continues
2:50 Break (20 minutes)
3:10 Session Five: High Performance DSP
4:05 Session Six: On Chip Interconnect for Multicore
5:00 Adjourn
Integrating two or more processor cores on a single chip is the hottest trend in high-performance microprocessor design. And it's not just for PCs and servers -- embedded processors are actually setting the pace, with some new designs boasting more than a hundred cores.

If you design chips or systems, you simply can't avoid multicore technology. If you're a programmer or system-software engineer, soon you'll face the challenge of writing or acquiring software for a multicore processor. The one conference where anyone interested in multicore integration can ramp up their knowledge is Fall Processor Forum 2005 (October 24 - 27, San Jose, California).

FPF 2005 will focus on three key topics: announcements of new multicore processors, technical presentations about products and technologies for multicore chip designers, and technical presentations about multicore software. Much of this information will be relevant to cutting-edge single-core designs, too.

For 18 years, our forums have been the leading international events for announcing new microprocessors and related technologies. In-Stat's Spring Processor Forum (formerly Embedded Processor Forum) and Fall Processor Forum (formerly Microprocessor Forum) are held annually in San Jose, California, attracting attendees and speakers from all over the world. Last year, In-Stat successfully launched Processor Forum Taiwan to reach more people in the fast-growing Asia-Pacific markets. All our forums are organized and moderated by the experienced analysts at Microprocessor Report, the leading newsletter for microprocessor technology.

Each forum has new announcements and technical disclosures about processors for desktop PCs, mobile PCs, servers, and embedded systems. Presentations are aimed at a technical audience and typically cover low-power technology, high-performance technology, network processors, extreme processors (radical designs), DSPs, DSP extensions, licensable processor cores, architectural extensions, reconfigurable/configurable processors, multicore architectures, and related topics. No other conference is so focused on the technology of microprocessors, and no other conference has the history and experience of our forums. The typical attendee is an engineer or engineering manager involved in a design project.