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Tuesday - October 25th
Keynote:
"What
Consumers Want: The Next Big Challenge in IC Design"
presented by Mike Fister, President & CEO, Cadence Design Systems
Session
One
Multicore Processors
Presented by Kevin Krewell, Editor in Chief, Microprocessor Report,
In-Stat
A traditional strength of Fall Processor Forum
is the premiere of interesting high-performance microprocessors.
This year we have cutting-edge presentations of multicore processors
that span the range from high-performance servers, portable media
devices, high-performance DSP applications, and general high-performance
processing. Most of these presentations will be the first public
disclosures of the chips.
"A
Concurrent Multi-Threaded Core for Complex SoCs"
presented by Kimming So, Senior Principal Scientist, Broadcom
"SPARC64
VI/VI+: Fujitsu's Next Generation Processor"
presented by Takumi Maruyama, Manager of Enterprise Server Development,
Fujitsu Limited
"The
IBM PowerPC 970MP - A New, Low-Power, High-Performance, Dual-Core
Processor"
presented by Norman Rohrer, IBM Distinguished Engineer
"Application
Customized CPU Design for Microsoft XBOX 360"
presented by Jeff Brown, IBM Distinguished Engineer, IBM Corporation
"A
Power-Efficient, Scalable Processor Family"
presented by Jim Keller, V. P. Engineering, Architecture Group,
P. A. Semi
Special
Presentation
"Multicore Processing - A Game Changing Innovation"
presented by Scott Sellers, Vice president of Hardware Engineering,
CTO and co-founder, Azul Systems
Session
Two
Innovative
IP
Presented by Tom R. Halfhill, Senior Analyst, In-Stat
Two companies will describe some particularly innovative
intellectual property (IP) in this session. A leading vendor will
disclose the first technical details about the microarchitecture
of its first superscalar embedded-processor core, and another company
will describe a new technology for integrating inexpensive memory
in microprocessors.
"A New ARM Low-Power Superscalar Processor
with Advanced SIMD Support"
presented by David Williamson, Consulting Member of Technical Staff,
ARM
"Z-Ram
and the Cinderella Effect"
presented by Mark-Eric Jones, CEO, Innovative Silicon
Session
Three
Processor IP for Multicore
Presented by Tom R. Halfhill, Senior Analyst, In-Stat
Multicore chips require processor cores suitable
for replication and mutual communication. This session includes
technical presentations from intellectual-property (IP) providers
that license embedded-processor cores designed for easier multicore
integration. Most of these presentations will describe previously
undisclosed products and technologies.
"ARC's
New Multi-Standard Multimedia Subsystem"
presented by Nigel Topham, Chief Architect,
ARC International
"A
Programmable, High-Performance Video Engine with Multiple Processor
Cores"
presented
by Gulbin A. Ezer, Hardware Design Manager, Tensilica
"A
Next-Generation Scalable Video Processor Core"
presented by Hans-Joachim Stolberg, Co-founder, CEO & CTO, videantis
GmbH
Wednesday - October 26th
Keynote:
"Software and the Concurrency Revolution"
presented by Herb Sutter, Software Architect, Microsoft Developer
Division
Session
Four
Building Systems with Multicore Processors
Presented
by Jim McGregor, Principal Analyst, In-Stat and
Kevin Krewell, Editor in Chief, Microprocessor Report, In-Stat
Building on the Multicore Processors for Computing
and Networking seminar held prior to the Spring Processor Forum,
this session will include technical presentations from selected
vendors on key topics surrounding the use of multicore processors
in system design, including asymmetric processing, software development
tools, and virtualization.
"Facing
the Software Challenges of Multicore Designs"
presented by Neil Puthuff, Director of Hardware Engineering, Green
Hills Software
"Xen
and the Art of Virtualizing Multi-core Platforms"
presented by Simon Crosby, V. P. of Strategy & Corporate Development,
XenSource
"Pacifica:
x86 Architectural Enhancements to Facilitate Virtualization"
presented by Kevin McGrath, AMD Fellow
"Asymmetric
Multiprocessing in a Dual-Core Processor"
presented
by Toby Foster, System Architect, Freescale
"Design
Considerations for the Cell Processor"
presented by Alex Chow, Manager, S-T-I Design Center and David Krolak,
Development Engineer, IBM
Session
Five
High-Performance
Digital Signal Processing
Presented by Max Baron, Principal Analyst, In-Stat
Presented by DSP market leaders, this session
will focus on achieving high-performance digital signal processing
via single and dual-core configurations. Details of hardware architecture
will be complemented by an overview of software tools and distribution
of workloads.
"StarCore
V5 Architecture"
presented by Amnon Rom CTO, V. P. Engineering, StarCore
"TMS320c672x
DSP Brings High Floating-Point Performance for Mainstream Audio"
presented by Amitabh Menon, CPU and SoC Architect, Texas Instruments
Session
Six
On-Chip Interconnect for Multicore
Presented by Tom R. Halfhill, Senior Analyst, In-Stat
Although processor cores attract most of the
attention focused on multicore chips, equally important are the
on-chip interconnects that allow the multiple processor cores to
rapidly communicate with each other and share resources. In this
session, the technical presentations will describe sophisticated
interconnect technology for multicore chips, including an unusual
solution based on asynchronous logic.
"GALS Interconnect: Delivering
Transparent Connectivity for Multi-Core SoCs"
presented by Uri Cummings, V. P. of Product Development, Fulcrum
Microsystems
"Licensable
IP for High-Performance On-Chip Interconnects"
presented by Drew Wingard, CTO, Sonics
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