Conference

Tuesday, May 17th

Keynote Speaker
Walden C. Rhines, CEO, Mentor Graphics

Session l — High-Performance Licensable-IP Processor Cores
Tom R. Halfhill, Senior Analyst, In-Stat
Licensable microprocessor cores are no longer limited to low-power embedded applications. Some of the latest IP cores deliver industry-leading performance while maintaining the flexibility of IP integration and, in some cases, core configurability. The innovative new cores presented in this session will raise the bars of performance and versatility.

Presentations

Silicon-Thrifty Floating-Point Extensions for ARC Processors
presented by Peter Wells, Director of Solution Architects, ARC International

XAP3: A New 32-Bit Processor Core with High Code Density
presented by Alistair Morfey, Technology Director, Cambridge Consultants Ltd.

The Massively Parallel D-Fabrix v2.0 Processor Core
presented by Alan Marshall, CTO, Elixent.

A High-Performance MIPS32 RISC Processor With DSP Enhancements
presented by Chinh Tran, Engineering Manager, MIPS Technologies, Inc.

The AVISPA Family of VLIW Parallel-Processing Cores for Multimedia and Communications
presented by Dr. Jeroen Leijten, co-founder and Chief Architect, Silicon Hive

MicroBlaze v4, An Enhanced 32-Bit Processor Core for FPGA Integration
presented by Ralph Wittig, Director, Embedded Processor Division, Xilinx

Session 2 — High-Performance Embedded Processors
Kevin Krewell, Editor-in-Chief, Microprocessor Report, In-Stat
A traditional strength of the Spring Processor Forum is the premier of interesting high-performance embedded microprocessors. This year is no different with cutting-edge and diverse presentations.

Presentations

Announcing the Newest Members of AMCC's PowerPC 440 Embedded Processor Family
presented by Xavier Bocquet, Senior Manager, Engineering, AMCC Embedded Products, AMCC

Feroceon: A Scalable, Low Power, High-Performance, and Low Cost Superscalar Processor Supporting the ARM ISA
presented by Dr. Sehat Sutardja, CEO and co-founder, Marvell Semiconductor, Inc.

Instruction Parallel Processor (IPP) Architecture on Panasonic Integrated Platform for Digital CE
presented by Masaitsu Nakajima, General Manager-Processor Development Group, Matsushita Electric Industrial Co., Ltd.

A Next Generation MIPS64 Multiprocessor
presented by David Hass, Principal Architect, Raza Microelectronics

Session 3 - Cool Processing Technologies
Jim McGregor, Principal Analyst, In-Stat
First introduced in Fall Processor Forum 2004, this track examines some of the unique processing technologies developed to increase performance, reduce power, and/or address the unique needs of certain market segments.

Presentations

UCC Mobile: A Programmable Demodulation Core for Multi Standard Handheld TV
presented by Peter McGuinness, Director of Business Development, Imagination Technology

The Design of a Multi-GHz Pipeline Control Unit using Fast14 Technology
presented by Terry Potter, Senior Member of Technical Staff, Intrinsity, Inc.

Kilocore: Low Power Parallel Computing on a Chip
presented by Dr. Andrew Singer, CEO & CTO, Rapport, Inc.

Niagara: Sun's Radical Realization of Chip MultiThreading
presented by William Bryg, Distinguished Engineer, Sun Microsystems

Introducing Tarari's multi-core, multi-function Content Processing ASIC
presented by Jeff Carmichael, V.P., Engineering & CTO, Tarari, Inc.

Wednesday, May 18th

Session 4 — Advances in DSP Engines
Max Baron, Principal Analyst, In-Stat
Whether for radio communications, cellular telephony or multimedia applications, digital signal processing is the fastest evolving branch of computing with multiple chip and core introductions by leaders and rising companies in the field. The seven presentations featured in this session cover among themselves cores, chips, multiprocessors and special purpose accelerators.

Presentations

Portable Media Architecture Implemented on OptimoDE
presented by Steve Steele, Business Development Manager, ARM

Advanced Memory Architecture of CEVA-X1621 VLIW/SIMD DSP
presented by Avi Davis, Senior DSP Architect, CEVA, Inc.

The MXC275-30 Edge Processor from Freescale Semiconductor
presented by Jose Corleto, Systems and Architecture Manager, Freescale Semiconductor

A Quad-MAC DSP Core Targeting Wireless Handset Applications
presented by Brendon Slade, Director, DSP Solutions Engineering, LSI LOGIC

Processor Network Executes Multimedia and Graphics
presented by Ron Hui, Director, InterQoS Systems, Ltd.

C55x+ Architecture Lowers Power, Increases Performance
presented by Jean-Pierre Giacalone, Distinguished Member of the Technical Staff, Texas Instruments

High-Performance C6xxx Architecture Targets Specific Applications
presented by Nat Seshan, Distinguished Member of Technical Staff, Texas Instruments

Special Presentation
Jim Kahle, IBM Fellow

Track 1 — Processing Engines for Video Applications Jeff Bier, BDTI Video applications make tough demands, combining high processing loads with tight cost and power constraints. This track highlights the processors--including off-the-shelf chips and licensable cores--that are rising to these challenges. Processors in this track use a variety of architectures to meet the demands of digital video, including RISC, DSP, and configurable solutions. These approaches are often combined to produce a heterogeneous architecture. Primary target markets: Surveillance, digital television, digital video cameras, digital video recorders, and other consumer video products. Presentations Stratix-II FPGAs as Cost-effective Video Engines presented by Brian Jentz, DSP Marketing Manager, Altera A High-Performance Multiprocessor DSP for Multimedia Infrastructure presented by Erik Machnicki, Architect, Cradle Technologies, Inc. A Scalable, Low-Power Processor for DTV Applications presented by Gerald Krottendorfer, CTO, ON DEMAND Microelectronics

Track 2 — Audio Extensions for Licensable Processor Cores Tom R. Halfhill, Senior Analyst, In-Stat This track offers technical presentations about digital-audio extensions and other solutions for licensable-IP embedded-processor cores. The extensions may include additional instructions or even coprocessor engines. Primary target markets: MP3 players, multifunction cellphones, set-top boxes, and other consumer-electronics products. Presentations Peter Wells, Director of Solution Architects, ARC International Travis Lanier, Product Manager, NEON Technology, ARM Radhika Thekkath, Director of Architecture, MIPS Robert Kennedy, Senior Software Engineering Manager, Tensilica

Panel — Soul of the New Benchmark:
Moderated by Kevin Krewell, Editor in Chief, In-Stat
Soul of the New Benchmark
An informal panel discussion on the latest challenges in benchmarking processors and systems.

Michael Goddard, Director, CPG Performance Labs, AMD
Jeff Bier, co-founder and General Manager, BDTi
Markus Levy, President, EEMBC
Tero Sarkkinen, Executive V.P., Sales and Marketing, Futuremark Corp.
Walter Bays, President, SPEC