Continental breakfast 8:00 am
Conference 9:00 - 5:00 pm (Gateway Ballroom, Second Level)
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presented by Dan Dobberpuhl, President and CEO, P.A. Semi, Inc.
A decade ago, Dan Dobberpuhl led the team that developed the first high-performance, low-power microprocessor - the original StrongARM chip. Most recently, he has led the development of the new PWRficient family of Power Architecture-based processors at P.A. Semi. In his keynote presentation, Dan will review the basic physics of power in integrated circuits, the design principles behind the StrongARM processor, and explain the evolution of those principles as applied to the latest 65nm technology and the design of the PWRficient family. From this background he will extrapolate to future generations of
microprocessors at 45nm and beyond. |
Session Four
This mega-session is split over two forum days and provides the core presentations for our theme of power-efficient design. The session addresses a range of technology tools available to chip designers. The session’s seven presentations include a tool to estimate the energy and power requirements of a configurable and extendable IP core, design techniques that save power from some of the best in the industry, an example of power/performance considerations in floor-planning and pin locations on the ARM Cortex-A8, and benchmarking a final product against its competitors.
Presentations
Improved Scalable Power Management Solutions
presented by Mike Olivarez, Principal Staff Scientist, Freescale Semiconductor, Inc.
New Core Enables Programmable Camera Sensor Signal Processing
presented by Jeroen Leijten, CTO, Silicon Hive
ARM Cortex-A8: Power-Aware, High-Performance Design
presented by Vivek Nagaraj, Implementation Lead, ARM
Power Reduction using LongRun2 in Efficeon Processors
presented by Dave Ditzel, Founder & CTO, Transmeta Corporation
Benchmark Methodology for Evaluating Processor Energy Costs and Performance
presented by Shay Gal-On, V.P., Software Engineering, EEMBC
presentation co-authored by Greg Crouch, Embedded Systems Business Development Director, National Instruments
Session Five
Digital video is one of the fastest-growing markets for embedded processors. The long-anticipated rise of HDTV and plunging prices of flat-panel displays are driving millions of consumers to buy new TVs for their homes. At the same time, trend-setting companies like Apple and Google are jump-starting a new market for portable video players and video downloads. The innovative video processors in this session include aggressive low-power designs for portable systems and a new massively parallel architecture for high-definition video processing.
Presentations
The CA1024: A Massively Parallel Processor for Cost-Effective HDTV
presented by Gheorghe Stefan, Chief Scientist, Connex Technology
A New Multicore Architecture for High Performance and Low Power
presented by Charles Moore, CTO, IntellaSys
Corporation
MuviStar: A New Video-Processor Architecture Using Custom Extensions
presented by Hans Volkers, Senior System Architect, sci-worx
Multicore Content Processors for Efficient HD-Video Encoding
presented by Jeff Carmichael, VP of Engineering , CTO & co-founder,Tarari, Inc.
Two New Video Processors for Portable Media Players and Digital TV
presented by Cary Ussery, President, CEO & Founder, Vivace Semiconductor, Inc.
Day One of the conference |
